ARM Cortex-M Programming Guide to Memory Barrier Instructions

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4.7. Enabling interrupts using CPS instructions and MSR instructions

In normal applications there is no need to add any barrier instruction after using a CPS instruction to enable an interrupt:

_enable_irq(); /* Compiles to “CPSIE I” - Clear PRIMASK */

If an interrupt was already in the pending state, the processor accepts the interrupt after the “CPSIE I” is executed. However, additional instructions can be executed before the processor enters the exception handler:

• for Cortex-M3 or Cortex-M4, the processor can execute up to TWO additional instructions before entering the interrupt service routine

• for Cortex-M0, the processor can execute up to ONE additional instruction before entering the interrupt service routine.

Figure 14 shows the implemented interrupt enabling delay in the Cortex-M3 and Cortex-M4 processors.

Figure 14. Implemented interrupt enabling delay in the Cortex-M3 and Cortex-M4 processors

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Figure 15 shows the implemented interrupt enabling delay in the Cortex-M0 and Cortex-M0+ processors.

Figure 15. Implemented interrupt enabling delay in the Cortex-M0 and Cortex-M0+ processors

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Architectural requirements

ARM recommends that the architectural requirements are adopted.

• If it is necessary to ensure a pended interrupt is recognized before subsequent operations, the ISB instruction should be used after CPSIE I. Figure 16 shows the use of the ISB instruction after enabling interrupts to permit immediate recognition of the pending interrupt.

• If it is not necessary to ensure that a pended interrupt will be recognized immediately before subsequent operations, it is not necessary to insert a memory barrier instruction.

• Between two time critical tasks, if you want to permit a pended interrupt to take place, you can use an ISB instruction as follows:

  __enable_irq(); // CPSIE I : Enable interrupt
  __ISB(); // Allow pended interrupts to be recognized
  __disable_irq(); // CPSID I : Disable interrupt
  

  Figure 16 shows the resulting behavior.

  Figure 16. Use ISB after enabling interrupts to permit immediate recognition of a pending interrupt

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  A suitable architectural coding is:

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  Figure 17 shows the resulting behavior.

  Figure 17. Architectural interrupt behavior between CSPIE and CPSID

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Note

The same requirement applies when using the MSR instruction to enable interrupts.

Implementation requirements

In Cortex-M processors:

• If it is necessary to ensure a pended interrupt is recognized before subsequent operations, the ISB instruction should be used after CPSIE I. This is the same as the architectural requirement, see Figure 16.

• If it is not necessary to ensure that a pended interrupt is recognized immediately before subsequent operations, it is not necessary to insert a memory barrier instruction.

• An exception to this rule is the sequence CPSIE followed by CPSID. In Cortex-M processors, there is no need to insert an ISB between CPSIE and CPSID.

  A suitable implementation coding is:

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Figure 18 shows the implemented behavior.

Figure 18. Implemented behavior requires no ISB between CPSIE and CPSID

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Note

As the implementation requirements show, there is no need to add a memory barrier instruction between __enable_irq() and __disable_irq(). However, in the architecture, if the interrupt needs to be recognized between the CPSIE and CPSID instructions, then an ISB instruction is needed. The same applies when using the MSR instruction to enable interrupts.